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SIGNAL PROCESSING TECHNOLOGIES
SPT
* * * * * * * * *
SPT2210
Y/C VIDEO ENCODER
APPLICATIONS
Video cameras Digital video tape recorders Video conference equipment Video frame grabbers Set-top boxes Video projection and displays Video printers Video game machines Multimedia PCs
FEATURES
* * * * * * * * * * * * * * Supports NTSC (M) and PAL (B, D, G, H, I) CCIR 601, square pixel and 4Fsc operation 4:2:2 YCrCb and 4:1:1 YCrCb digital input formats Two on-chip 8-bit video DACs Internally generates SYNC and color burst signals Internal vertical interpolation filter Analog composite or Y/C output High-resolution mode supports Video CD, V2.0 16 CLUT RAM (programmable) Four modes of video/graphics operation: graphics, video, chroma key and external key Color bar generation test function Suspend function 64-lead PQFP package Single +3.3 V power supply
GENERAL DESCRIPTION
The SPT2210 is a single-chip video encoder that is capable of converting digital video data (YCrCb) into analog NTSC or PAL video signals. Two digital input formats are supported: 4:2:2 (YCrCb) and 4:1:1 (YCrCb). It internally generates the proper SYNC and color burst signals for NTSC (525 lines/60 Hz) and PAL (625/50 Hz) video standards operating in any one of three sample rate modes: CCIR 601, square pixel and 4Fsc. Composite or Y/C S-Video analog video output is generated via two 8-bit internal video DACs. In addition, the SPT2210 supports external or chroma key functions for color graphics pixel-by-pixel overlay. It has a 16-color lookup-table overlay palette which is fully programmable. It also has an on-chip vertical interpolation filter that can be activated to reduce jaggy noise and flicker. The chip also features an internal test color bar pattern generator. The SPT2210 operates from a single +3.3 V supply and is built in a 0.5 m CMOS process. It is available in a 64lead PQFP package and operates over the commercial temperature range.
Suspend BLANK
BLOCK DIAGRAM
Field
CBF
CLK
H
SYNC Generator VCS YD7...0 Vertical Interpolation Vertical Interpolation
Y
V
MUX
Y
Level Converter
Cr Cb
Y
SYNC/BLANK Pedestal LPF
DAC DAC VREF
Y/CVBS C
CD7...0
Cr Cb
MUX
Interpolation Interpolation
Cr Cb
LPF
VRTENB
MUX DTO
GD3...0
CLUT 16 x 16
Y Cr Cb
MPU Interface
KEY
KEY Logic
CS RS RD WR D7...0 Reset
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
GENERAL DESCRIPTION OF FUNCTIONS
VIDEO MODES The SPT2210 supports NTSC and PAL video standards in Y/C (4:2:2) and Y/C (4:1:1) input formats. Table I shows the video modes supported. Table I - Supported Video Modes Video Mode NTSC Square Pixel Y/C (4:2:2/4:1:1) NTSC CCIR 601 Y/C (4:2:2/4:1:1) NTSC 4Fsc Y/C (4:2:2/4:1:1) PAL Square Pixel Y/C (4:2:2/4:1:1) PAL Square Pixel Y/C (4:2:2/4:1:1) PAL CCIR 601 Y/C (4:2:2/4:1:1) PAL 4Fsc Y/C (4:2:2/4:1:1) Active Number of Pixels 640 x 483 720 x 483 768 x 483 640 x 573 768 x 573 720 x 573 948 x 573 Input Clock Frequency 12.2727 MHz 13.5000 MHz 14.3182 MHz 12.1875 MHz 14.7500 MHz 13.5000 MHz 17.7345 MHz
HOST INTERFACE The operational modes and parameters of the SPT2210 can be changed via a MPU host parallel interface. The following parameters can be changed: * Low-pass filter * Switching between Y/C output and composite output * Switching between two's complement or offset binary data format * Selecting between seven video modes * 50%, Y, Y/C and color enable/disable * Color bar test pattern * Color kill (monochrome only out) * Graphics mode control * Software reset * Select Y/C 4:2:2 or 4:1:1 input format * Change of the Cr/Cb sampling order * Interpolation field changeover * Vertical interpolation filter bypass * Free run or reset of subcarrier phase * Turn off/on NTSC setup * Suspend mode * Input logic polarity set * V Blank_ timing adjust * H Blank_ timing adjust EXTERNAL SETTING PINS In addition to host interface control, the SPT2210 can be operated independent of host interface using external pin control. The external pin controls available are listed below: * Select between seven video modes * Sync/Blank I/O mode * Output of the built-in color bars * Free run or reset of subcarrier phase * Switching between Y/C output and composite output * Turn off/on NTSC setup See the External Setting Pin Descriptions section for operation.
VERTICAL INTERPOLATION The SPT2210 has a vertical interpolation filter that is used to reduce jaggy noise and flicker. It also supports the high-resolution mode for Video CD, version 2.0. TWO-CHANNEL D/A CONVERTER OUTPUT Digital video signals are output on two 8-bit D/A converters. Y/C (S-Video) output or composite video output can be selected. The Y/C video outputs are current sources, capable of driving a 75 load to 1 VP-P, referenced to ground. If both composite and S-Video are required simultaneously, a simple circuit (using the SPT9400 video driver) may be added. FOUR-BIT TITLE/GRAPHICS MULTIPLEXING FUNCTION Graphics from a 16-entry color lookup table can be arbitrarily displayed. In chroma mode it is possible to superimpose graphics and video input by specifying transparent colors. In the external key mode it is possible to display graphics in the areas specified pixel by pixel.
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Table II - Y/C Video Encoder Pin Functions
Signal Pin Name Numbers YD7...0 CD7...0 CBF BLANK_ FIELD V H KEY GD3...0 VRTENB 1-8 57-64 11 12 16 13 14 17 18-21 15 I/O I I I I I I/O I/O I I I I O O I I Function Luminance Digital Input (YD0 = LSB) (TTL Level) Color Difference Digital Input (CD0 = LSB) (TTL Level) Cr/Cb Sampling Order Control (TTL Level) External Blanking Control Signal Input (TTL Level) Field Indicator Signal (TTL Level) Vertical Synchronization Signal Input (TTL Level) Horizontal Synchronization Signal Input (TTL Level) Keying Signal Input (TTL Level) CLUT Ram Address (GD0 = LSB) (TTL Level) Vertical Interpolation Enable (TTL Level) Suspend Mode Enable/Disable Luminance or Composite Video Analog Signal Output (1 VP-P) Chrominance Video Analog Signal Output (1 VP-P) (Includes burst) Internal D/A Reference Voltage Input Internal D/A Output Signal Amplitude Control Voltage Address/Data Bus (TTL Level) Chip Select (TTL Level) Register Select (TTL Level) Read from Data Bus (TTL Level) Write to Data Bus (TTL Level) Reset Signal Input (TTL Level) System Clock Input (Pixel Clock) Test Mode Enable/Disable +3.3 V Power Supply for Digital Circuitry +3.3 V Power Supply for Analog Circuitry Ground for Digital Circuitry Ground for Analog Circuitry
DESCRIPTION OF PIN FUNCTIONS
DIGITAL VIDEO INPUTS AND CONTROLS YD7...0 Pins The luminance signal digital data is input on YD7...0 (TTL level). The input can be in either offset binary or two's complement format. The range of the input data is bounded from 16 to 235. Any data less than 16 is converted to 16 and data greater than 235 is converted to 235. The active pixels will be output after completion of the back porch as shown in figure 2. YD7 is the MSB and YD0 is the LSB. CD7...0 Pins The color difference digital data is input on CD7...0 (TTL level). The input can be in either offset binary or two's complement format. The input range of the offset binary mode is from 16 to 240, and the input range of the two's complement mode is from -112 to +112. Signal data is bounded to these minimum and maximum limits. As a means of dealing with abnormal data, color kill is carried out when 00(H) of FF(H) is detected for two successive clocks or more at CD7...0 (automatic color kill mode). Color kill is immediately cancelled when data other than 00(H) or FF(H) are entered. The order of Cr and Cb is determined by the combination of the CBF pin (described below) and the Cr/Cb inversion bit, D2 (data bit 2), of the command register CR1. In normal setup mode (Cr/Cb inversion bit = 0 and CBF pin = 1) and 4:2:2 format, the input is started with the Cb data and, after that, Cr and Cb are repeated alternately. (Refer to figure 1.) In the 4:1:1 format only (with normal CBF setup) the first and the second data positions in time are used, and the third and fourth data are ignored (or not present). (Refer to figure 1.) The first data is repeated again after the fourth data. The active pixels are output after the back porch as shown in figure 2. CD7 is the MSB and CD0 is the LSB. CBF Pin This is the Cr/Cb control pin. It determines the sampling order of Cr/Cb. When the command register CR1, data bit 2, (Cr/Cb inversion) is low (clear), the CBF pin is input as positive true logic. (See the Command Register Descriptions.) When CBF is high, the SPT2210 samples the data as Cb after the leading edge of HSYNC_ and the back porch has occurred. When CBF is low, the SPT2210 samples the data as Cr after the leading edge of HSYNC_ and the back porch has occurred. When the command register CR1, data bit 2, (Cr/Cb Inversion) is high (set), the CBF pin is input as negative logic. (See the Command Register Descriptions.) In this mode the CBF pin is read as inverted.
Digital Video Inputs and Controls
SUSPEND 43 Video Outputs Y C VREF VCS 53 49 46 47
MPU Interface and Clock D7...0 29-32,36-39 I/O CS_ RS RD_ WR_ RESET_ CLK TEST 22 23 24 25 26 34 42 I I I I I I I
Power Supply Connections VDD 10,28,35,41,56 AVDD 44,52 -
GND 9,27,33,40,55 AGND 45,48,54 -
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Figure 1 - Y/C Data Input Format (CBF=High, CR1:D2=0)
HSYNC_
YD7...0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
CD7...0
Cb1
Cr1
-
-
Cb5
Cr5
-
4:1:1 Format HSYNC_
YD7...0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
CD7...0
Cb1
Cr1
Cb3
Cr3
Cb5
Cr5
Cb7
4:2:2 Format
Figure 2 - Y/C Data Input Timing
HSYNC_
YD7...0 CD7...0
Effective Pixels Back Porch Front Porch
Operation Mode NTSC CCIR 601 NTSC Square Pixel NTSC 4Fsc PAL CCIR 601
Number of Effective Pixels 720 Clocks 640 Clocks 768 Clocks 720 Clocks
Back Porch 122 Clocks 120 Clocks 124 Clocks 132 Clocks 152 Clocks 164 Clocks 120 Clocks
Front Porch 16 Clocks 20 Clocks 18 Clocks 12 Clocks 24 Clocks 23 Clocks 20 Clocks
PAL Square Pixel (14.75) 768 Clocks PAL 4Fsc 948 Clocks
PAL Square Pixel (12.18) 640 Clocks
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Figure 3 - Set of BLANK_ Terminal and Display/Nondisplay
HSYNC_
Internal Blank
Blank_
Nondisplay
Nondisplay
Display
Nondisplay
Display
Nondisplay
Blank_ Pin This is the input pin for the external blanking control signal (TTL level). The SPT2210 samples BLANK_ at the rising edge of CLK. When BLANK_ is high, the output proceeds with normal operation and when it is low the output signal gets blanked (i.e., no display). The specification of the blank state can be performed on a pixel-bypixel basis. The chip has an internal blanking function that operates independent of the external blanking signal. Figure 3 shows operation of the internal blanking in conjunction with external blanking. Table III delineates the internal blanking that is generated regardless of the level of the blank pin, upon detection of HSYNC_. Table III - Internal Blanking Periods for NTSC and PAL
NTSC Lines Lines Line(s) 1 to 20 263 to 283 525 PAL 1 to 23 310 to 335 623 to 625
Figure 4 - Sync Signal Input Timing
VSYNC_
HSYNC_ Odd Numbered Field
VSYNC_
HSYNC_
Even Numbered Field
V Pin This input pin provides the timing to generate the vertical signal out of the SPT2210. The mode of operation for this pin is controlled by Command Register, CR5. The sampling of the sync signal occurs on the rising edge of clock. When the Vsync input signal is asserted during an Hsync signal the field is considered to be odd, else the field is even. (Refer to figure 4.) When in the blank operational mode the field is determined by the field input signal.
H Pin This input pin provides the timing to generate the horizontal signal out of the SPT2210. The mode of operation for this pin is controlled by Command Register, CR5. The sampling of the sync signal occurs on the rising edge of clock. When the timing for Hsync/Hblank input is different from the number of clock cycles shown in table IV, the phase of the subcarrier will be put into free-run. Since the horizontal blanking period in Figure 2 is determined internally, the width and the trailing edge of HSYNC_ are not detected. The active pixels are output after the completion of the back porch as shown in figure 2.
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Table IV - Expected Line Clock Count for Various Modes
Video Mode NTSC 4Fsc NTSC Square Pixel NTSC CCIR 601 PAL 4Fsc PAL Square Pixel (s = 14.75 MHz) PAL Square Pixel (s = 12.1875 MHz) PAL CCIR 601 Clocks 910 780 858 1135 944 780 864
VRTENB Pin This is the vertical interpolation enable signal input pin (TTL level). When VRTENB is high, vertical interpolation is enabled and when it is low, vertical interpolation is disabled. N/C Pins These are no connect pins. VIDEO OUTPUTS Y Pin This is the luminance or composite analog output signal pin. The Y output pin is a current source capable of driving a 75 load terminated to ground to 1 VP-P. The encoded analog luminance or composite signal is output on this pin. C Pin This is the chroma analog output signal pin. The C output pin is a current source capable of driving a 75 load terminated to ground to 1 VP-P. The chroma signal is output on this pin. VREF Pin This is the reference voltage input pin for the internal D/A converters. A 0.1 F capacitor and voltage divider of 6.8 k and 5.1 k resistors should be connected to this pin from +3.3 V. VCS Pin This is the control voltage for the output amplitude of the internal D/A converters. The D/A output amplitude can be adjusted from 1.0 to 1.4 VP-P using this pin. MPU INTERFACE AND CLOCK D7...0 Pins These are the address and data input/output bus pins (TTL level). This is a bidirectional 8-bit bus. D7 is the MSB and D0 is the LSB. When the CS_ (chip select) pin is high, the D7...0 bus is in a high impedance state. The SPT2210 features the ability to run without an external MPU host. In this mode, D7...0 and RS (Register Select) pins can be used as external mode setting pins. The D7...0 pins and RS pin become external setting pins when CS_, RD_ (Read Enable) and WR_ (Write Enable) are low for three clock cycles or more. Refer to the External Setting Pin Descriptions section for more details. CS_ Pin This is the chip select input pin (TTL level). The SPT2210 is selected for read/write operation when this pin is low. The CS_ pin is also used in enabling the external pin mode. Refer to the External Setting Pin Descriptions section for more details.
FIELD This is an input signal controlled by CR5. It is sampled on the leading edge of the clock cycle. It indicates the field odd or even and is required in the Blank mode. High level indicates ODD and low level indicates EVEN field. TEST This is an input signal. During normal operation it is set to a logic low. Test functions of the device are enabled by taking this pin to a logic high. SUSPEND This input pin is set to a logic low for normal operation. When set to a logic high, the SPT2210 suspends operation and no output is active. This includes taking in data from either the MPU data ports or video data. KEY Pin This is the external key input pin (TTL level). Input from this pin is enabled when the external key mode is activated by setting the command register CR1 bits to D1 = 1 and D0 = 1. (See the Command Register Descriptions section.) When KEY is high, the colors of the contents of color lookup table (CLUT) that is specified by means of GD3...0 are displayed. When KEY is low, the data of YD7...0 and CD7...0 are output. This mode is called the external key mode. GD3...0 Pins These are the graphic data input pins (TTL level). This 4-bit input port specifies which one of the 16 color entries in the CLUT is to be output for the current pixel. If GD3...0 is all low when the SPT2210 is in chroma mode, the CLUT output is transparent and the data of the YD7...0 and CD7...0 ports are output. (This assumes that the transparent color was not changed in Address 0H of the CLUT.) Refer to the Color Lookup Table (CLUT) Description section.
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RS_ Pin This is the register select input pin (TTL level). The D7...0 pins operate as either address or data registers (except when operating as external setting pins). The RS_ pin determines the mode in which D7...0 will operate. When RS_ is low the D7...0 bus is switched to the address bus mode, and when it is high the bus is switched to the data bus mode. The RS_ pin is also used as an external pin in the external pin mode. Refer to the External Setting Pin Descriptions section for more details. RD_ Pin This is the read enable input pin (TTL level). The data on D7...0 is read out of the SPT2210 on the leading edge of a high-to-low transition of RD_. If RS_ is high, the data is read from the internal register specified by the last address write. If RS_ is low, the current address value is read from the address register. The RD_ pin is also used in enabling the external pin mode. Refer to the External Setting Pin Descriptions section for more details. WR_ Pin This is the write enable input pin (TTL level). The data on D7...0 is written into the address or command register on the leading edge of a high-to-low transition of RD_. If RS_ is high, the data is written into the internal command register specified by the last address write. If RS_ is low, the data is written into the address register. The WR_ pin is also used in enabling the external pin mode. Refer to the External Setting Pin Descriptions section for more details. Reset Pin This is the reset input pin (TTL level). The reset input is sampled on the leading edge of the system clock (CLK). The SPT2210 is initialized by holding the RESET_ pin low for a minimum of five clock cycles. The SPT2210 will come out of reset five clock cycles after the RESET_ pin has been brought back high. CLK Pin This is the system clock input pin (TTL level). The YD7...0, CD7...0, GD3...0, BLANK_, V, H, Field and KEY pins are all sampled on the rising edge of the CLK signal. Additionally, when an asynchronous access from the MPU is processed, the access is synchronized with this clock and then the processing is carried out. When the clock is switched over to another operating frequency (i.e., changing video modes), the SPT2210 should be reset once to ensure proper operation. In this case, the command registers will need to be set again. VDD Pins These are the +3.3 V power supply pins for the digital circuitry.
AVDD Pins These are the +3.3 V power supply pins for the analog circuitry. VDD and AVDD are completely independent of each other. Be sure to keep the following operating condition: | VDD - AVDD | 0.5 V. GND Pins These are the ground pins for the digital circuitry. AGND Pins These are the ground pins for the analog circuitry. Since GND and AGND are completely independent of each other, it is necessary to keep them at the same electric potential by externally tying them together through a ferrite bead. Internal Pullup and Pulldown Resistors The following pins are either pulled up or down with an internal resistor of approximately 100 k: Pins with internal pulldown: CD7...0, YD7...0, GD3...0, KEY, VRTENB, TEST, SUSPEND. Pins with internal pullup: RESET_, BLANK_, V, H, CS_, RD_, WR_, D7...0, CBF, RS, CLK.
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Figure 5 - Typical Interface Circuit
VDD
0.1
VDD
4.7 F 0.1
AVDD
4.7 F
Blank_ V H Video Data 3.3 V Buffer 8 8 YD7...0 CD7...0 CLK CS_ MPU Interface 3.3 V Buffer 8 WR_ WR_ RD_ RD_ RS RS D7...0 D7...0 Reset_ Reset_
VDD
AVDD GD3...0 Key
900 75
5
Graphics Control SPT9400
LPF 4.7 F
Y
33 F 75 33 F 75 33 F 75
Y CVBS C
SPT2210
C
900 75
LPF
4.7 F
VREF
1.4 V typ 6.8 k 0.1 5.1 k
AVDD
Suspend
VRTENB
GND
CBF
Test
AGND
VCS
2.7 k 0.1 1 k
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REGISTER FUNCTIONS
GENERAL DESCRIPTION There are two general types of registers in the SPT2210. One type is a command register and the other is a color lookup table (CLUT). Table V shows the register mapping for both types of registers. A third register is the address register that enables access to command registers and the CLUT. Table V - Register Map
Address 00H 01H 02H 03H 04H 05H 06H 07-0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Register Name Command Register 1 Command Register 2 Command Register 3 Suspend HV I/O HV Timing Background Control Reserved CLUT Entry 0 CLUT Entry 1 CLUT Entry 2 CLUT Entry 3 CLUT Entry 4 CLUT Entry 5 CLUT Entry 6 CLUT Entry 7 CLUT Entry 8 CLUT Entry 9 CLUT Entry 10 CLUT Entry 11 CLUT Entry 12 CLUT Entry 13 CLUT Entry 14 CLUT Entry 15 Default Value 02H 01H 00H 00H 00H 00H 00H ---00,80,80 Transparent 28,70,F0 100% Blue 50,F0,58 100% Red 6C,E0,C8 100% Magenta 90,20,38 100% Green A8,10,A8 100% Cyan D0,90,10 100% Yellow EC,80,80 100% White Not Used 1C,78,B8 50% Blue 30,B8,70 50% Red 40,B0,A8 50% Magenta 50,50,58 50% Green 60,48,90 50% Cyan 74,88,48 50% Yellow 80,80,80 50% White
COMMAND REGISTER DESCRIPTIONS Tables VI through XV give detailed descriptions for programming the SPT2210 command registers.
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COMMAND REGISTER DESCRIPTIONS
COMMAND REGISTER CR1 CR1 (Address = 00H)
D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB
Table VI - Command Register CR1 Description Table
Address Bit # 00H 7 Function Software reset Bit Setting /Description 0 Normal operation 1 Reset; all registers returned to default 0 Normal operation 1 Color test bar is generated 0 Use fixed at 0 1 0 Use fixed at 0 1 0 Normal operation 1 Monochromatic (black and white) image is output 0 According to the order specified by the CBF pin 1 According to the order specified by the inverted CBF pin See table VII Default 02H
6 5 4 3
Test bar Not used Not used Color kill
2
Cr/Cb inversion
1,0
Chroma key control. Set multiplex mode of YD7...0 and CD7...0 video input, and GD3...0 graphics input
Table VII - Multiplexing Mode (Command Register 1)
D1 0 0 1 D0 0 1 0 Mode Graphics Mode Video Mode Chroma Key Mode Operation GD3...0 is displayed irrespective of the KEY terminal pin state. The transparent color cannot be specified in this mode. YD7...0 and CD7...0 are always selected irrespective of the state of the KEY terminal. YD7...0 and CD7...0 are displayed only at the parts in which transparent colors are specified by means of GD3...0. GD3...0 is displayed in all other parts. YD7...0 and CD7...0 are displayed when the KEY terminal pin is set to logic 0. GD3...0 is displayed when the KEY terminal is set to logic 1. Transparent colors cannot be specified in this mode.
1
1
External Key Mode
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COMMAND REGISTER DESCRIPTIONS
COMMAND REGISTER CR2 CR2 (Address = 01H)
D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB
Table VIII - Command Register CR2 Description Table
Address Bit # 01H 7 6 5 4 Function Low pass filter bypass (U/V filters) Not used Not used Composite video enable Bit Setting /Description 0 Enabled 1 Disabled (bypassed) 0 Use fixed at 0 1 0 Use fixed at 0 1 0 Component mode: Luminance signal output through the Y pin 1 Composite mode: Composite signal output through the Y pin 0 Offset binary 1 Two's complement See table IX Default 01H
3 2,1,0
Color data format on CD7...0 Video mode selection
Table IX - Video Mode (Command Register 2)
D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Operation Mode NTSC 4Fsc NTSC square pixel NTSC CCIR 601 525/60 Setting disabled PAL 4Fsc PAL square pixel, S = 14.7500 MHz PAL CCIR 601 625/50 PAL square pixel, S = 12.1875 MHz
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COMMAND REGISTER DESCRIPTIONS
COMMAND REGISTER CR3 CR3 (Address = 02H)
D3 D2 D1 D0 MSB LSB
Table X - Command Register CR3 Description Table
Address Bit # 02H 7-4 3 2 Function Not used Odd/even vertical interpolation field Vertical interpolation bypass Bit Setting /Description Fix at 0 0 Start at ODD field 1 Start at EVEN field 0 Normal operation 1 Vertical interpolation is bypassed 0 Subcarrier phase is reset every odd frame 1 Subcarrier free run (i.e., not reset) 0 Setup enabled 1 No setup Default 00H
1
Phase free run (NTSC only)
0
Setup enable (NTSC only)
SUSPEND REGISTER (Address = 03H)
D0 MSB LSB
Table XI - Suspend Register Description Table
Address Bit # 03H 7-1 0 Function Not used Suspend mode Bit Setting /Description Fix at 0 0 Normal operation 1 Suspend Default 00H
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COMMAND REGISTER DESCRIPTIONS
H/V I/O REGISTER (Address = 04H)
D4 D3 D2 D1 D0 MSB LSB
Table XII - H/V I/O Register Description Table
Address Bit # Function 04H 7-5 Not used 4 Field polarity Bit Setting /Description Fix at 0 0 Positive logic. High level = Odd field 1 Negative logic. High level = Even field V signal (VSYNC and VBLNK) polarity 0 Positive logic 1 Negative logic H signal (HSYNC and HBLNK) polarity 0 Positive logic 1 Negative logic Blank I/O 0 HBLNK/VBLNK/FIELD output mode 1 HBLNK/VBLNK/FIELD input mode Timing I/O 0 HSYNC/VSYNC input mode 1 HBLNK/VBLNK/FIELD I/O mode Default 00H
3 2 1
0
H/V TIMING REGISTER (Address = 05H)
D6 D5 D4 D3 D2 D1 D0 MSB LSB
Table XIII - H/V Timing Register Description Table
Address Bit # 05H 7 6-5 Function Not used Vertical Blank timing Bit Setting /Description Fix at 0 00 1V=240H 01 1V=241H 10 1V=242H 11 Not used See table XIV Default 00H
4-0
Horizontal Blank timing
Table XIV - Horizontal Blank Timing Control (H/V Timing Register)
D4....D0 01111 01110 * * * 00001 00000 HBLNK Timing +15 clocks from the original point. +14 clocks from the original point. * * * +1 clock from the original point. +0 (Default: original point) D4....D0 10001 10010 * * * 11110 11111 HBLNK Timing -1 clock from the original point. -2 clocks from the original point. * * * -14 clocks from the original point. -15 clocks from the original point.
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COMMAND REGISTER DESCRIPTIONS
BACKGROUND CONTROL (Address = 06H)
D1 D0 MSB LSB
Table XV - Background Control Description Table
Address Bit # 06H 7-2 1 Function Bit Setting /Description Not used Fix at 0 Half Y/C and 50% Color Enable. 0 Half Y/C and 50% Color Input Y value is reduced by 50% and Disable C is replaced with CLUT15 Cb/Cr data 1 Half Y/C and 50% Color Enable Half Y/C Enable. Input Y/C value is 0 Half Y/C Disable reduced by half. 1 Half Y/C Enable Default 00H
0
ACCESSING THE COMMAND REGISTERS Access to the command registers for read or write purposes is performed in the following sequence. It requires the correct setting of the control lines and setting the data on the bidirectional 8-bit data bus. Command Register Read and Write Operation Address Setup: Set CS_, RS low. Set the data bus to the address required, then set WR_ low. Set WR_ high, then CS_ and RS high. This completes the address write and points to the register that may be read from or written to. Register Read: After completing address setup, Set CS_ low, RS high. Set RD_ low, this enables the data from the pointed-to register onto the data bus. Set RD_, CS_ and RS high. This completes the register read operation; subsequent reads from the same register may be performed, if the address has not been changed.
Register Write: After completing address setup, set CS_ low, RS high. Set the data required onto the data bus, then set WR_ low. Set WR_, CS_ and RS high, then release data bus input data. This completes the register write operation; subsequent writes to the same register may be performed, if the address has not been changed.
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COLOR LOOKUP TABLE (CLUT) DESCRIPTION
CLUT FORMAT AND DATA LIMITS The CLUT has 16 entries and is set up in YCrCb threebyte format. (See below.) The upper 6 bits in the Y data are used (lower two are filled with zero) and the upper 5 bits in the Cr/Cb data are used (lower 3 bits are filled with zero). Therefore the setting ranges are Y = 00H to FCH (midpoint value = 80H) and Cr and Cb = 00H to F8H (midpoint value = 80H). The numerical values of Cr and Cb are expressed in offset binary form, irrespective of the setting of bit D3 in Command Register 2. Since no limit processing is carried out in connection with the CLUT data entries, it is necessary to set Y within the limits of 16 to 236 (10H to ECH) and Cr/Cb within the limits of 16 to 240 (10H to F0H).
Bit composition of Y (address=10H~1FH) D7 D6 D5 D4 D3 D2 MSB 0 0 LSB 1st Byte
values of Y, Cr and Cb are given by the following calculations: Y = 0.2990 x 120 + 0.5770 x 96 + 0.1140 x 96 = 102 Cr = 0.5000 x 120 - 0.4187 x 96 - 0.0813 x 96 +128 = 140 Cb = 0.1684 x 120 - 0.3316 x 96 + 0.5000 x 96 + 128 = 124 Since the SPT2210 CLUT only uses the upper 6 bits in the Y data and the upper 5 bits in the Cr/Cb data, it is necessary to round the results above. The second bit is rounded in the Y calculation and the third bit is rounded in the Cr and Cb calculation. The results are shown below: Y = 102 = 01100110 (binary) results in 01101000 (binary) = 104 Cr = 140 = 10001100 (offset binary) results in 10010000 (offset binary) = 144 Cb = 124 = 01111100 (offset binary) results in 10000000 (offset binary) = 128 ACCESSING THE COLOR LOOKUP TABLE The method for accessing the CLUT is different from the method for accessing the command registers because each entry of the CLUT has a length of 3 bytes at each address. The CLUT is accessed by means of three successive bytes after writing the address. Note that Y, Cr and Cb cannot be accessed individually in the CLUT. They must be accessed in units of three bytes sequentially. Color Lookup-table Register Read and Write Operation Address Setup: Set CS_, RS low. Set the data bus to the address required (10H - 1FH), then set WR_ low. Set WR_ high, then CS_ and RS high. This completes the address write and points to the CLUT registers that may be read from or written to. Register Read: After completing address setup, Set CS_ low, RS high. Set RD_ low; this enables the data from the pointedto register onto the data bus (first byte, Y data). Set RD_ high, then set RD_ low; this enables the data from the pointed-to register onto the data bus (second byte, Cr data). Set RD_ high, then set RD_ low; this enables the data from the pointed-to register onto the data bus (third byte, Cb data). Set RD_, CS_ and RS high. This completes the three-byte sequence of CLUT register read operation at the specified address.
Bit composition of Cr (offset binary, address=10H~1FH) D7 D6 D5 D4 D3 MSB 0 0 0 LSB 2nd Byte
Bit composition of Cb (offset binary, address=10H~1FH) D7 D6 D5 D4 D3 MSB 0 0 0 LSB 3rd Byte
TRANSPARENT COLOR Transparent colors can be used in chroma key mode (See Combining Video and Graphics Signals for more details.) Transparent colors can be entered in the CLUT with the following data values for Y, Cr and Cb: Y = 00H, Cr = 80H, Cb = 80H When these data values are selected in the CLUT, the graphics data becomes transparent and the SPT2210 displays the video YD7...0 and CD7...0 data instead. COLOR SPACE CONVERSION FROM RGB TO YCRCB FOR CLUT ENTRY The SPT2210 CLUT stores data in YCrCb format only. RGB graphics data must be converted in the host before loading the CLUT. The conversion for RGB to YCrCb is shown here: Y = 0.2990 x R + 0.5770 x G + 0.1140 x B Cr = 0.5000 x R - 0.4187 x G - 0.0813 x B +128 Cb = 0.1684 x R - 0.3316 x G + 0.5000 x B + 128 Example: Assume that each RGB data is 8 bits in length and that their values are R = 120, G = 96, B = 96. The
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Register Write: After completing address setup, set CS_ low, RS high. Set the data required onto the data bus, then set WR_ low and then back high; this will write the Y data. Set the data required onto the data bus, then set WR_ low and then back high; this will write the Cr data. Set the data required onto the data bus, then set WR_ low and then back high; this will write the Cb data. Set WR_, CS_ and RS high, then release data bus input data. This completes the three-byte sequence of the CLUT register write operation at the specified address.
Figure 6 - Multiplex in Chroma Mode
GD3...0 (Except transparent color) YD7...0, CD7...0 +
GD3...0 (Transparent)
GD3...0
YD7...0 CD7...0
COMBINING VIDEO AND GRAPHICS SIGNALS
EXTERNAL KEY MODE The external key mode is selected by setting the command register CR1, bits D1...0 = 11 (binary). In this mode it is possible to combine the video signals (YD7...0, CD7...0) with the graphics signals (GD3...0). When the KEY pin is high, in conformity with the timing shown in figure 8, the graphics signals (out of the CLUT and referenced by GD3...0) are output (i.e., displayed). This can be done on a pixel-by-pixel basis. CHROMA MODE The chroma key mode is selected by setting the command register CR1, bits D1...0 = 10 (binary). In this mode the graphics signal image becomes the front image, and the Y/C image becomes the rear image. The Y/C image is displayed in the portions of the display in which the transparent colors are specified in the graphics image data stream. Figure 6 illustrates the combining of video and graphics images in the chroma mode.
VERTICAL INTERPOLATION The SPT2210 has a vertical interpolation filter that is used to reduce jaggy noise and flicker. It also supports the high resolution mode for Video CD, version 2.0. INTERPOLATION FIELD SELECTION The vertical interpolation filter is active for each odd or even field as specified in command register CR3, bit D3. However, vertical interpolation is not active for NTSC line 21 and PAL line 25 when the ODD field is selected (CR3, bit D3 = 0) and NTSC line 285 and PAL line 336 when the EVEN field is selected (CR3, D3 = 1). INTERPOLATION BYPASS Vertical interpolation is automatically enabled and disabled for the proper even/odd field depending on the field selection specified in CR3, bit D3. The VRTENB pin enables interpolation, in conjunction with the even/odd field algorithm, as shown in figures 7 and 8. The interpolation filter may be bypassed altogether by setting bit D2 in command register CR3 or setting the VRTENB pin to logic low.
Figure 7 - Vertical Interpolation Timing CR3 D2=0, D3=1; Even Field
Even HSYNC_ VSYNC_ VRTENB Vertical Interpolation Bypass Bypass Active Bypass Bypass Bypass Odd Even Odd Even Odd
Figure 8 - Vertical Interpolation Timing CR3 D2=0, D3=0; Odd Field
Even HSYNC_ VSYNC_ VRTENB Vertical Interpolation Bypass Active Bypass Active Bypass Bypass Odd Even Odd Even Odd
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EXTERNAL SETTING PIN DESCRIPTIONS
The SPT2210 has the capability of operating without a host interface and allowing certain programmable settings to be accessed via external pins. When the RD_, WR_ and CS_ pins are all held (or tied) low for a minimum of three clock pulses, the D7...0 bus and the RS pin can be used for external setting of various modes and functions. (When these pins are not used as external setting pins, they are ordinary pins for host interface.) Table XVI below shows the pin function assignments and settings for the D7...0 and RS pins.
Figure 9 - Multiplexing in the External Key Mode
HSYNC Key
Key VSYNC
YD7...0 CD7...0
GD3...0
Table XVI - D7...0 and RS Pin External Setting Description Table
Pin # D7 D6 D5 Function Composite video mode Color bars Phase reset (NTSC only) Bit Setting 0 1 0 1 0 1 D4,3 SYNC/BLNK I/O D4 0 0 1 1 D2 0 0 0 0 1 1 1 1 D3 0 1 0 1 D0 0 1 0 1 0 1 0 1 Description Y/C (S-Video) Composite video Normal operation Generate color bars Subcarrier phase is reset at every odd frame Free run; subcarrier phase is not reset SYNC, BLNK, I/O BLNK Input SYNC Input BLNK Output Reserved Mode NTSC 4Fsc NTSC Square Pixel NTSC CCIR 601 525/60 Setting disabled PAL 4Fsc PAL Square Pixel (S=14.7500 MHz) PAL CCIR 601 625/50 PAL Square Pixel (S=12.1875 MHz) Setup enabled No setup
D2...0
Video mode setting
RS
Setup (NTSC only)
D1 0 0 1 1 0 0 1 1 0 1
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ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C
Supply Voltages VDD ......................................... VSS -0.3 to VSS +4.6 V AVDD ...................................... VSS -0.3 to VSS +4.6 V Input/Output Voltages Digital Inputs .......................... VSS -0.3 to VDD +0.3 V Digital Outputs ....................... VSS -0.3 to VDD +0.3 V Temperature Operating Temperature .............................. 0 to 70 C Junction Temperature ..................................... 150 C Lead Temperature (soldering 10 seconds) ..... 300 C Storage Temperature ......................... -40 to +125 C
Note:1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA = +25 C, AVDD=VDD=+5.0 V, unless otherwise specified. PARAMETERS Analog Outputs Differential Linearity Integral Linearity Output Full-Scale Current Digital Inputs Reset Pin VIH VIL IIH IIL Digital Outputs VOH VOL Power Supply VDD AVDD VDD-AVDD IDD TEST CONDITIONS TEST LEVEL MIN TYP MAX 0.5 1.0 13 UNIT LSB LSB mA
0.7 x VDD VIH = VDD VIL = VSS IOH = -4 mA IOL = 4 mA -10 -10 2.4 0.4 3.0 3.0 -0.5 VDD=+3.3 V , =17.73 MHz 10 10 10 10 1 X TCC 1 X TCC 3 3 10 10 56 20 20 10 10 5 X TCC 25 20 20 50 3.6 3.6 +0.5 0.3 x VDD 10 10
V V A A V V V V V mA ns ns ns ns
Timing Characteristics CS Setup (TCSS) CS Hold (TCSH) RS Setup (TRSS) RS Hold (TRSH) RDWR_ Pulse Low (TRWL) RDWR_ Pulse High (TRWH) Delay to Data Bus Valid (TDBV) CL=50 pF Output Data Delay Time (TDLY) CL=50 pF Data Output Disable (TDOD) Data Output Hold (TDOH) Write Data Setup (TWDS) Write Data Hold (TWDH) Clock Cycle (TCC) Clock Pulse High (TCH) Clock Pulse Low (TCL) Input Data/Cont Setup (TIS) Input Data/Cont Hold (TIH) Reset Pulse Width (TRSW)
ns ns ns ns ns ns ns ns ns ns ns ns
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TEST LEVEL CODES
All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
TEST LEVEL
I II III IV V VI
TEST PROCEDURE
100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range.
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Figure 10 - MPU Interface Timing
TCSS TCSH
CS_
TRSS
TRSH
RS_
TRWL TRWH
RD_, WR_
TDOD TDBV TDOH
D7...0 (READ)
TWDS TWDH
D7...0_
Figure 11 - AC Data Timing
TCC TCL CLK TCH
TIS INPUT DATA: H, V, FIELD, BLANK, YD7...0, CD7...0, GD7...0, KEY, SUSPEND, VRTENB
TIH
TDLY OUTPUT DATA: H, V, FIELD
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PACKAGE OUTLINE
64-LEAD PQFP
G A B
64 49
INCHES SYMBOL A MIN 0.465 0.390 0.017 0.006 MAX 0.480 0.398 0.023 0.010
MILLIMETERS MIN 11.80 9.90 0.42 0.15 7.5 typ 11.80 1.40 0.125 0-10 12.20 1.70 0.132 MAX 12.20 10.10 0.58 0.26
1
48
B C D E
EF
Index
0.295 typ 0.465 0.055 0.0049 0.480 0.067 0.0052
F G H
16
33
I J 0.012 0.000
0-10 0.028 0.008 0.30 0.00
0.70 0.20
17
C
D
32
K
H
K
J I
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PIN ASSIGNMENTS
AGND N/C AVDD GND VDD CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 N/C C
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 YD0 YD1 YD2 YD3 YD4 YD5 YD6 YD7 GND VDD CBF BLANK_ V H VRTENB FIELD
Y
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AGND VCS VREF AGND AVDD SUSPEND TEST VDD GND D0 D1 D2 D3 VDD CLOCK GND
SPT2210
RESET_
D7 VDD
D6
D5
D4
CS_
RD_
ORDERING INFORMATION
PART NUMBER SPT2210SCT DESCRIPTION Y/C Video Encoder TEMPERATURE RANGE 0 to +70 C PACKAGE TYPE 64L PQFP
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited. WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
KEY
RS
GD3
GD2
GD1
GD0
WR_
GND
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